The international application WO2006/012503A2 discloses a BIST (Build In Self Test) scheme for functionality tests of analog circuitry such as frequency response, gain, cut-off frequency, signal-to-noise ratio and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (which in the following is referred to as DDS) as the test pattern generator which can generate various test waveforms such as chirp, ramp, step frequency, two-tone frequencies, sweep frequencies, MSK (Minimum Shift Keying), phase modulation, amplitude modulation, QAM (Quadrature Amplitude Modulation) and other hybrid modulations. A digital to analog converter (DAC) converts the digital test signals into an analog test signal to be supplied to the analog device under test (which in the following is referred to as DUT). The BIST scheme utilizes a multiplier followed by an accumulator as the output response analyser.
The publication “A BIST Architecture for Sigma Delta ADC testing Based on Embedded NOEB Self-Test and CORDIC Algorithm” of N. Chouba and L. Bouzaida at 2010 International Conference on Design & Technology of Integrated Systems in Nanoscale Era, IEEE Conference Publications 10.1109/DTIS.2010.5487558 (978-1-4244-6340-4/10) discloses a BIST architecture for testing a sigma-delta ADC. The BIST architecture comprises a binary stream generator which generates a 2252 bits periodic binary sinusoidal stimulus to be supplied to the analog input of the sigma-delta ADC to be tested. A CORDIC generates the reference signal to be used by the modified sine wave fitting in comparing the digital output signal of the sigma-delta ADC with the reference signal.
These prior art test signal generators require a significant amount of extra chip area,